Steady-state analysis of the clock synchronizer for a narrowband communication system†

Abstract

The bit synchonizer consists of the cascade of a low pass filter (LPF), a nonlin-earity (NL) and a phase-locked loop (PLL) for the narrowband communication system. In this paper an analysis is given by means of the transform method and the harmonics representation of a cyclostationary process. It is found that the bandwidth of the LPF should be chosen carefully so that the retrieved clock signal has phase closely matching that of the received pulse train for a given type of LPF and NL. From the viewpoint of minimizing the phase variance of the clock signal, the second order NL is better than the full wave rectifier by about 2dB. In contrast with the carrier synchronizer, the average power spectrum of the NL output is not flat near zero frequency. Hence, conventional PLL theory does not apply for the design of the PLL in the clock synchronizer.