Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration

Abstract

Subthreshold circuit has the significant advantage in low-power applications but suffers from serious variation increase. Traditional EDA tools could not achieve balance between accuracy and simulation effort for statistical timing analysis in subthreshold region. Many researches have been devoted to statistical timing model to reveal the relation between delay variation and process variation with physical insight. However, the statistical correlation of gate delay in circuit path is hard to capture and not considered appropriately in most prior works. In this paper, a statistical timing model for subthreshold circuit is proposed with the consideration of local process variation and correlated variation from adjacent gates, which is established by deriving variance models for gate delay and output waveform analytically for fast and slow input waveform separately, so that the path delay variation can be translated from the accumulation of the correlated gate delays with input slew to a linear combination of independent step input delays. The proposed model was verified under the process of TSMC28nm technology at the subthreshold supply voltage with the estimation error of less than 6% for circuit path delay variation in benchmark ISCAS99 compared with Monto Carlo simulation results, which outperforms prior works with 5∼10X accuracy increase and acceptable simulation cost.