A Statistical Timing Model for Low Voltage Design Considering Process Variation

Abstract

Near-threshold voltage (NTV) design suffers severe challenge due to the dramatic increase in performance uncertainty introduced by process variation. This paper proposes an analytical approach based on Log-Normal (LN) distribution to characterize the statistical delay for NTV design considering the dominant threshold voltage variation from gate-level to circuit-level. At gate-level, the multivariable threshold voltage variation issue is solved by the equivalent threshold voltage method and equivalent drain current method for generic gates with stack topology and parallel topology, respectively. At circuit-level, a statistical timing model is proposed as the linear combination of the independent statistical delays of all gates in the path with step input by considering the varied correlation between adjacent gates. To the best of our knowledge, we firstly propose a statistical timing model analytically for practical circuit path with physical insights of supply voltage, transistor size, and load capacitance. The characterization effort for each path is only one-time SPICE simulation, which is negligible compared with Monte Carlo (MC) simulation in statistical static timing analysis (SSTA) methods. Experimental results under a commercial 28-nm CMOS process show the proposed models have high accuracy at low supply voltage compared with MC simulations, where the modeling errors for the mean and variance of gate delay can be limited within 1.54% and 11.2%, respectively. Moreover, as for the practical paths in ITC'99 benchmark, the maximum modeling errors of mean, variance, minimum delay, and maximum delay is less than 3.04%, 11.40%, 4.50%, and 2.87%, respectively.