Statistical Test Development for Analog Circuits Under High Process Variations

Abstract

The test development efforts for analog circuits today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement setup requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric and catastrophic faults into the circuit and analyzing the masking effect of process variations, we develop a fault injection and simulation technique for analog circuits that is specifically geared toward information reuse. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on several circuits confirm the high accuracy of our variance analysis technique and show a nearly 72% reduction in the number of tests for a three-stage amplifier circuit in the experiment after the application of the test selection algorithm.