Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

Abstract

We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.