Abstract
This paper presents an electrical characterization and a compact modeling of FD-SOI four-gate qubit MOS devices, carried out at room temperature and in linear regime. The main figures of merit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.
Highlights
The Fabrication of spin quantum bits has been recently demonstrated from an industrial Silicon-On-Insulator (SOI) CMOS platform [1], [2], [3], marking an important first step for the fabrication of a quantum computer in Si
The extraction was performed exploiting the Y-function method [12], [16], which is immune to series resistance effect
The main device parameters have been extracted from average drain current curves using the Y(VG) − function method
Summary
The Fabrication of spin quantum bits has been recently demonstrated from an industrial Silicon-On-Insulator (SOI) CMOS platform [1], [2], [3], marking an important first step for the fabrication of a quantum computer in Si. The importance of room temperature characterization of qubit devices relies on technological benchmarking. Characterization and modeling of MOS devices at deep cryogenic temperatures are mostly performed on mature technologies [8], [9], [10], [11]. To the best of our knowledge, no characterization or compact model has ever been developed for multi-gate structures like the one presented in this work. We present a complete room temperature electrical and statistical characterization of new FD-SOI four-gate MOS devices, designed to be functionally qubits at very low temperatures. The parameters previously extracted were used to fit the data with a Lambert function based compact model, that allows to reconstruct the full device electrical characteristics from weak to strong inversion regimes
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