Abstract
Timing errors become dominant in dynamic performance of high-speed and high-resolution current-steering digital-to-analog converters (DACs). To improve the dynamic performance and relax the requirements of timing errors in circuit/layout design, a mapping technique, based on on-chip timing error measurement, was proposed. This mapping technique can significantly improve the dynamic performance, no matter if timing errors are interconnection-related or mismatch-related. Matlab simulation results show that the spurious-free dynamic range (SFDR) is improved, e.g. 30dB for linearly distributed interconnection-related timing errors and 10dB for randomly distributed mismatch-related timing errors.
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