Abstract
In this paper, signal integrity (SI) analysis of a high bandwidth memory (HBM) interposer channel is conducted based on proposed statistical analysis and modeling method. Parallel simultaneous switching output buffers generating large power/ground noise are considered based on the statistical approach which enables efficient SI analysis. Impacts of the power distribution network (PDN) design and data coding such as data bus inversion on the SI of the HBM interposer channel are discussed.
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