Statistical Analyses of Digital Phase-Locked Loops with Time Delay

Abstract

In this correspondence, first it is pointed out that introducing time delay of one sampling interval in digital phase-locked loop considerably eases restriction on operating times of digital circuits in the loop. Then statistical analyses are performed for first- and secondorder loops with time delay of one sampling interval in order to see the effect of the time delay on their performances. Approximate analytic expressions are obtained for the steady-state phase error probability density and phase error variance, and their validity is confirmed by numerical analysis. Increase in the phase error variance due to the introduction of the time delay is found to be of tolerable order for sufficiently high input SNR, and thus the delayed sampling scheme proposed here is considered to be effective in easing the restriction on the operating times of the digital circuits in the loop.