Abstract
Standard cells are commonly used for current design processes for digital circuits' creation. They are already created and optimized blocks and using them fastens the process of designs, improves chip's parameters and manufacturability. However, standard cell and the library needs to be verified throughout the all steps starting from the cell layout to the design placement and route. Although there are different methods to test and verify standard cell libraries, they are paying less attention to some of the verification aspects or are ignoring them at all. Hence, a novel approach to standard cell library validation is presented, which is considering logic cells' and physical only cells abutment check, including well tap cells, end cap cells and filler cells. By this, standard cell library is being verified not only from the logic perspective but also from the physical and cell abutments. Based on the experiments using 14nm open access libraries, the method can achieve about ∼11% more cell coverage in comparison with existing methods because of special standard cell logic synthesis and physical placement and routing implementation. However, because of cell placement's special requirements, the tool runtime increases about 23,3%.
Published Version
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