Abstract
New stacking cell design topologies are introduced in this article to achieve effective electrostatic discharge on-chip protection while meeting relatively high-holding-voltage and low-trigger-voltage characteristic requirements. A resistive silicon-controlled-rectifier (SCR) device forming the stacking structures is initially presented, which combines resistive and SCR-like current-voltage characteristics. By embedding this resistive SCR along with the existing optimized low-holding-voltage baseline devices, the overall stacking structure can achieve the requirement of high current-handling capability and high-holding-voltage tolerance without increasing the trigger voltage.
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