Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs

Abstract

Due to the inherent nature of heat flow in 3-D integrated circuits, stacked dies exhibit a wide range of thermal characteristics. The temperature of dies progressively increases with increasing distance from the heat sink. This heterogeneous temperature profile coupled with the strong dependence of leakage on temperature and process variation plays havoc in achieving system level energy efficiency in such systems, complicating the task of power provisioning in 3-D multicores. In this paper, we address this power provisioning challenge in 3-D ICs by advocating a novel stack aware microprocessor design paradigm, where the circuit designers are aware of the intended placement of a die in a 3-D stack. We present a concrete application of this paradigm through a stack aware threshold voltage (Vt) assignment algorithm for a 3-D multicore system, where we specifically account for: 1) the change in the role of leakage power; 2) expected operating frequency; and 3) dependency of PV induced leakage variation and Vt levels. Our stack aware scheme tunes Vt assignment based on the vertical placement of the die in a 3-D stack. Detailed simulation based experiments with our proposed algorithm show 4%-19% improvement in energy efficiency for a typical multicore system organized as 3-D stacked dies.