A Novel Threshold Voltage Assignment for 3D Multicore Designs

Abstract

Chips organized in a 3D stack exhibit widely varying thermal characteristics, driven by the fundamental principles of heat flow. This heterogeneous thermal profile, in conjunction with the strong dependence of leakage with temperature and process variation, imposes a severe challenge of power provisioning in 3D multicore systems. In this paper, we propose a novel physical design paradigm for 3D multicore systems, where circuit level optimizations are guided by the knowledge of the intended placement of a die in the 3D stack. We illustrate this design paradigm using a concrete example of a threshold voltage (V t ) assignment algorithm for a 3D multicore. Our algorithm integrates the impact of temperature dependent leakage in thermal provisioning, expected variation in thermal profile of a 3D multicore, and the dependency of V t levels on PV induced leakage variation. Rigorous evaluation based on detailed architectural simulation demonstrates 2-15% improvement in energy efficiency of a typical 3D multicore system using our proposed technique.