SRAM read performance degradation under asymmetric NBTI and PBTI stress: Characterization vehicle and statistical aging data

Abstract

Asymmetric BTI aging in circuit paths has shown to cause a time dependent shift in the signal's duty cycle, affecting the performance of circuits such as low power SRAMs whose operation rely on both the positive and negative edges of the clock signal. In this work, we propose the first known on-chip reliability monitor to accurately characterize the impact of asymmetric BTI on SRAM read speed. Statistical data collected from test chip built in a 32nm high-k metal-gate technology shows that (i) the average SRAM read frequency decreases with stress while its variation increases with stress and (ii) both µ and σ of read frequency shift follow a power law dependence on stress time. These observations point to the impact of SRAM peripheral circuit aging on read performance, and the utility of the proposed monitor for characterizing circuit level reliability concerns.