Abstract
An SRAM (static random access memory)-based reprogrammable FPGA (field programmable gate array) is investigated for space applications. A new commercial prototype, named the RS family, was used as an example for the investigation. The device is fabricated in a 0.25 /spl mu/m CMOS technology. Its architecture is reviewed to provide a better understanding of the impact of single event upset (SEU) on the device during operation. The SEU effect of different memories available on the device is evaluated. Heavy ion test data and SPICE simulations are used integrally to extract the threshold LET (linear energy transfer). Together with the saturation cross-section measurement from the layout, a rate prediction is done on each memory type. The SEU in the configuration SRAM is identified as the dominant failure mode and is discussed in detail. The single event transient error in combinational logic is also investigated and simulated by SPICE. SEU mitigation by hardening the memories and employing EDAC (error detection and correction) at the device level are presented. For the configuration SRAM (CSRAM) cell, the trade-off between resistor dc-coupling and redundancy hardening techniques are investigated with interesting results. Preliminary heavy ion test data show no sign of SEL (single event latch-up). With regard to ionizing radiation effects, the increase in static leakage current (static I/sub CC/) measured indicates a device tolerance of approximately 50 krad(Si).
Highlights
The antifuse FPGA has gained significant visibility in recent years as the programmable logic device choice for space applications
Without introducing a process hardening technique, or employing single event upset (SEU) mitigation techniques, the utilization of SRAM-based FPGAs will be prohibitive for many space applications
This paper presents results of the investigation of an SRAM-based FPGA for its radiation performance and potential enhancement
Summary
The antifuse FPGA has gained significant visibility in recent years as the programmable logic device choice for space applications. The development and radiation effects for FLASH-based FPGAs will be published elsewhere (see reference [ 1]). Without introducing a process hardening technique, or employing SEU mitigation techniques, the utilization of SRAM-based FPGAs will be prohibitive for many space applications. There have been serious efforts to develop a viable, radiation-hard SRAM-based FPGA. This paper presents results of the investigation of an SRAM-based FPGA for its radiation performance and potential enhancement. A commercial prototype, named the RS product family is used as the starting point Both SEE (single event effects) and total ionization dose (TID) effects areinvestigateFd.ocusis ontheSEUof memorbyitsin the device. The Actel product presented in this paper is called RS It is fabricated on the advanced 0.25!am CMOS technology in commercial foundries.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have