Speedup of bit-parallel Karatsuba multiplier in [formula omitted] generated by trinomials

Abstract

In this letter, we present a speedup of bit-parallel Karatsuba multiplier in GF ( 2 m ) generated with a class of irreducible trinomials. Applying a slightly modified Karatsuba approach, we can save one XOR gate delay at the cost of little increase of space complexity. The proposed multiplier has a lower time complexity than the previous Karatsuba multipliers except for those based on equal-space trinomial or all-one polynomial. In counterpart it only requires one more XOR time delay than the best known multipliers for trinomials but maintains a smaller number of logic gates.