Abstract
As the traditional 2-D scaling is approaching its physical limit, there is a great motivation to explore the third dimension for future integrated circuit design. The memory industry has already adopted monolithic 3-D integration (e.g., in 176-layer 3-D NAND Flash), while the 3-D vertical integration structure of logic transistors (e.g., 3-D stacked nanosheets, NMOS on top of PMOS) is emerging for sub-3-nm logic nodes. The other trend is to stack the embedded nonvolatile memories [e.g., resistive random access memory (RRAM), phase change memory (PCM), magnetic random access memory (MRAM), and ferroelectric field-effect-transistor (FeFET)] on top of CMOS using the back-end-of-line (BEOL) processing. Taking one step further, the integration of multiple tiers of active transistors with embedded memories is expected to offer significant improvements in the throughput and energy efficiency thanks to the massive connectivity between logic and memories. Besides the technological breakthroughs, circuit design automation methodologies have become key enablers to optimize the tier partitioning in monolithic 3-D architectures. In addition, heat dissipation should be taken care of by accurate thermal modeling in these monolithic 3-D architectures. New heat spreading materials and advanced embedded cooling techniques are also important.
Highlights
1) monolithic 3-D transistors and their circuit and system implications; 2) BEOL compatible transistors; 3) BEOL compatible memories (e.g., resistive random access memory (RRAM), phase change memory (PCM), magnetic random access memory (MRAM), and FeFET); 4) computing-in-3-D NAND or 3-D NOR Flash; 5) silicon recrystallization methods for top tiers; 6) monolithic 3-D integration fabrication methods; 7) prototypes of monolithic 3-D circuit primitives (e.g., 3-D SRAM); 8) design automation of monolithic 3-D architectures (e.g., electronic design automation (EDA) flow for 3-D physical layout); 9) thermal modeling and simulations of monolithic 3-D architectures; 10) heat spreading materials and embedded cooling for monolithic 3-D architectures; 11) system-level design and benchmarking for monolithic 3-D architectures; 12) system-circuit-device co-design for energy-efficient monolithic 3-D architectures
The monolithic 3-D integration could embrace sequential processing as well as the layer transfer and die stacking as long as the inter-via density is high (>106/mm2). This Special Topic of the IEEE JOURNAL ON EXPLORATORY SOLID-STATE COMPUTATIONAL DEVICES AND CIRCUITS (JXCDC) called for the recent research advances in the area of the monolithic 3-D integration spanning from materials/devices toward circuits/architectures for energyefficient computing
After the open submission and a rigorous peer-reviewed process, seven articles were selected for this Special Topic
Summary
1) monolithic 3-D transistors and their circuit and system implications (e.g., complementary FET, NMOS on top of PMOS); 2) BEOL compatible transistors (e.g., based on semiconducting oxides or 2-D materials); 3) BEOL compatible memories (e.g., RRAM, PCM, MRAM, and FeFET); 4) computing-in-3-D NAND or 3-D NOR Flash; 5) silicon recrystallization methods for top tiers; 6) monolithic 3-D integration fabrication methods (e.g., layer transfer, sequential processing, and nano-TSV); 7) prototypes of monolithic 3-D circuit primitives (e.g., 3-D SRAM); 8) design automation of monolithic 3-D architectures (e.g., electronic design automation (EDA) flow for 3-D physical layout); 9) thermal modeling and simulations of monolithic 3-D architectures; 10) heat spreading materials and embedded cooling for monolithic 3-D architectures; 11) system-level design and benchmarking for monolithic 3-D architectures; 12) system-circuit-device co-design for energy-efficient monolithic 3-D architectures. Special Topic on Monolithic 3-D Integration for Energy-Efficient Computing
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