Special Issue on Design of Circuits and Integrated Systems

Abstract

This paper addresses the Network-on-Chip (NoC) application mapping problem. This is an NP-hard problem that deals with the optimal topological placement of Intellectual Property cores onto the NoC tiles. Network-on-Chip application mapping Evolutionary Algorithms are developed, evaluated and optimized for minimizing the NoC communication energy. Two crossover and one mutation operators are proposed. It is analyzed how each optimization algorithm performs with every genetic operator, in terms of solution quality and convergence speed. Our proposed operators are compared with state-of-the-art genetic operators for permutation problems. Finally, the problem is approached in a multi-objective way. Besides energy minimization, it is also aimed to map the cores such that a thermally balanced Network-on-Chip design is obtained. It is shown, through simulations on real applications, that by using domain-knowledge, our developed genetic operators increase the algorithms’ performance. By comparing these Evolutionary Algorithms with an Optimized Simulated Annealing, it is shown that they perform better. In the case of two contradictory objectives, our genetic operators can still help at providing the mappings with the lowest communication energy.