Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

Abstract

This paper introduces a new coding scheme that simultaneously tackles different design issues of interconnections such as noise, crosstalk and power consumption. The scheme is based on temporal skewing between data words on even and odd lines of an interconnection link, and its hardware implementation is simple and area-efficient. The proposed scheme permits to double the bandwidth of the interconnect while improving its noise tolerance. This is achieved through the simultaneous use of two error detecting techniques: temporal redundancy and parity. Improved noise tolerance property provided by our design enables to decrease the power supply voltage and hence to reduce power consumption of the interconnect.