Spatially Resolved Dielectric Loss at the Si/SiO_{2} Interface.

Abstract

The Si/SiO_{2} interface is populated by isolated trap states that modify its electronic properties. These traps are of critical interest for the development of semiconductor-based quantum sensors and computers, as well as nanoelectronic devices. Here, we study the electric susceptibility of the Si/SiO_{2} interface with nm spatial resolution using frequency-modulated atomic force microscopy. The sample measured here is a patterned dopant delta layer buried 2nm beneath the silicon native oxide interface. We show that charge organization timescales of the Si/SiO_{2} interface range from 1-150ns, and increase significantly around interfacial traps. We conclude that under time-varying gate biases, dielectric loss in metal-insulator-semiconductor capacitor devices is in the frequency range of MHz to sub-MHz, and is highly spatially heterogeneous over nm length scales.