Spatially distributed successive approximation register (SDSAR) photonic ADCs based on phase-domain quantization

Abstract

We explore photonic ADC architectures based on encoding voltage-under-test into phase. The first step is to identify two basic optical building blocks: the optical phase comparator (1-bit ADC), based on interferometric comparison of phases in the well-known balanced photo-detection configuration, and the optical 1-bit DAC, namely electro-optic modulation with a bipolar electrical pulse. Equipped with these fundamental building blocks, we proceed to systematically port and adapt known ADC quantization architectures to photonic ADC, conceiving a hybrid between the Successive Approximation Register (SAR) and the Pipeline classic ADC architectures, referred to here as Spatially Distributed SAR (SDSAR). This novel photonic ADC, constructed out of B 1-bit ADCs and B-2 1-bit DACs, with B the number of bits, is not equivalent to any of the previous photonic ADCs in the literature, but appears superior to prior schemes in both optical power efficiency and electro-optic modulation complexity. We derive upper bounds on resolution, Effective Number of Bits (ENOB) performance as a function of average optical power for the new SDSAR device, developing analytic and numeric Monte-Carlo statistical models, comprising quantization, shot, thermal and DAC voltage noise sources. Our findings indicate that SDSAR is limited to ~11.5 ENOBs, assuming state-of-the-art mode-locked-lasers providing ~250 mW of average power (assuming ~7 dB excess losses). However, this upper bound is not tight, due to various physical impairments. In particular, the mode locked laser jitter is shown to have negligible impact on overall performance for RMS jitter < 20 fsec.