Abstract
Space vector pulsewidth modulation (SVPWM) algorithms for cascaded H-bridge multilevel (CHB ML) inverter usually provide the possibility of using several combinations of active voltage vectors to generate the same output voltage vector. For preselected H-bridges, some of them may generate output voltages opposite to the assumed direction. This results in the change of the dc-link voltages of these H-bridges in the opposite direction to the assumed direction in the ordering algorithm. Consequently, these algorithms are characterized by undue constraints and narrow possibilities of dc-link voltage balancing. In the proposed control algorithm, CHB ML inverter is treated as groups of successively activated three-level inverters; depending on the length of the reference voltage vector. These three-level inverters consist of three H-bridges selected from each phase. The proposed extended selection method enables firm-grip control of the dc-link voltages. For a given direction of phase currents, the possibility of using H-bridges with lowest and highest dc-link voltages is simultaneously analyzed. Additionally, each of the three-level inverters is controlled by one of three proposed alternative modulation methods for which both the attainable output voltage vectors and unbalanced dc-link voltages are predicted. Simulation and experimental results confirm the correctness of the algorithm execution.
Highlights
cascaded H-bridge (CHB) inverters are popularly deployed in power electronic transformer applications, [1], [2], [3], static synchronous compensator (STATCOM) [4], [5] energy storage system, [6], [7], [8]
The results presented prove that by relatively small modification of the Space Vector Pulse Width Modulation (SVPWM) algorithm presented in [1], it is possible to reduce the voltage fluctuations on the dc-link capacitors
In CHB inverters with SVPWM strategies, the dc-link voltages are equalized by appropriate selection of negatively or positively connected H-bridges, where the ordering of the H-bridges used in the syntheses of the output voltage waveform depends on the direction of the power in a phase leg [15], [19]
Summary
THE growing popularity of multi-level inverters is due to the possibilities of generating output voltage magnitudes exceeding the blocking voltage ratings of the constituting semiconductor devices and obtaining output voltage/current waveforms similar to sinusoids. In CHB inverters with SVPWM strategies, the dc-link voltages are equalized by appropriate selection of negatively or positively connected H-bridges, where the ordering of the H-bridges used in the syntheses of the output voltage waveform depends on the direction of the power in a phase leg [15], [19]. It is worth noting that the multilevel CHB inverter with more than one H-bridge in each of the phases can be treated as a group of three-level inverters In this case, subsequent groups of three-level inverters are activated when the needed output voltage is more than and cannot be generated within the previous triangle in the space vector diagram, SVD, shown in the Figure 2. Where uref is a reference voltage vector to be generated in a multilevel CHB inverter, uout is the output voltage vector of the first three-level CHB inverter, uref is the output voltage vector to be generated in the three-level inverters, as proposed in [1]
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