Space compression revisited

Abstract

This paper discusses new space compression techniques for built-in self-testing (BIST) of VLSI circuits based on the use of compact test sets to minimize the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information, utilizing the concepts of Hamming distance, sequence weights along with failure probabilities of errors in the selection of specific gates for merger of output streams from the CUT. The outputs coming out of the space compactor may eventually be fed into a time compressor to derive the signature for the circuit. The concepts are extended to establish generalized mergeability criteria for merging an arbitrary number N of output bit streams under conditions of both stochastic independence and dependence of line errors. The proposed techniques guarantee rather simple design with high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable area overhead. Design algorithms are also proposed, and the simplicity and ease of implementation are demonstrated with examples, primarily through extensive simulation runs on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST. The paper also provides performance comparisons of the designed space compactors with conventional linear parity tree space compressor.