Realizing ultimate compression with acceptable fault coverage degradation to reduce MISR size in BIST applications by nonexhaustive test patterns

Abstract

In this paper we describe a space compression technique for realizing ultimate compression in multiple-input signature registers (MISRs), commonly used in built-in self-test (BIST) applications. The technique uses nonexhaustive test sets and is based on the inherent properties of the output sequences of a circuit under test (CUT) and the failure probabilities. The proposed technique guarantees a very high fault coverage for single stuck-line faults, with low CPU simulation time, and acceptable hardware overhead. Extensive simulation runs on ISCAS 85 combinational benchmark circuits with ATALANTA and COMPACTEST confirm the novelty of the suggested approach under conditions of both stochastic independence and dependence of single and double line errors.