Some aspects concerning design for e-beam testability

Abstract

Electron beam testing has become a powerful inspection technique for integrated circuits under operation, since an electron beam can act as a non-loading and non-damaging probe which can easily be adressed to any node of the circuit. A successful application of e-beam testing to integrated circuits of higher complexity, however, necessitates modifications of both test equipment and device layout. Essential developments of the testing set-up include use of bright electron beam guns, improvement of electron energy spectrometers and more sensitive signal processing. Furthermore a hybrid test system connecting a CAD design system equipment for VLSI and an e-beam tester has to be established indispensibly in order to obtain exact and automated probing of these nodes by the electron beam. However, there is also a demand for a modified circuit layout being appropriate to e-beam testing due to the following aspects: • - By theoretical treatment the influence of enlarged surfaces of test points on the achievable test duration has to be quantified. • - Numerical simulations quantitatively demonstrate the importance of circuit internal shielding electrodes in the direct vicinity of the probed node on the minimization of measurement errors caused by cross talk from neighbouring conductor tracks. Such calculations are treated for various parameters, such as device geometry, potential distributions and types of electron energy spectrometers. • - Extending the application of e-beam testing to the analysis of passivated devices by means of the capacitive coupling voltage contrast, this method may be strongly falsified by inhomogenous coupling of the local potential distributions at the metallization-passivation-interface with the passivations surface towards vacuum. Testing of multi-level-interconnection-devices is even more influenced by such falsifications and by this only possible for certain device geometries. From the results reported in this paper design rules can be deduced guaranteeing a sufficient e-beam testability for future integrated circuits.