Solving the Yield Optimization Problem for Wafer to Wafer 3d Integration Process

Abstract

Three dimensional integrated circuits (3D ICs) that stack multiple dies vertically using Through Silicon Vias (TSVs) have gained wide interests of the semiconductor industry. Fabricating these 3D ICs using wafer to wafer stacking has several advantages including: high throughput, high TSV density... However, one of the major challenges of the wafer to wafer stacking approach is the low compound yield. Various techniques have been presented in the literature to address this important problem. This paper investigates the compound yield improvement for wafer to wafer stacking method. To solve this problem, we propose two approaches: mathematical multi-dimensional axial assignment model using ILP and matching pre-tested wafers based Tabu search algorithm method. We focus on the performance of these two algorithms to solve the problem within an interesting running time and maximum yield. Finally, we present the results of our thorough computational study. The obtained results and the comparison with other algorithms show that our two algorithms gives better solutions.