Solving critical issues in 10nm technology using innovative laser-based fault isolation and DFT diagnosis techniques

Abstract

Failure Analysis (FA) and Design for Testability (DFT) diagnosis play a key role during first silicon bring up, helping identify critical test, design marginality and process issues in a timely and efficient manner. However, as the process technology continues to scale from 28 nm to 10nm FinFET, challenges arisen during FA, as the conventional electrical fault isolation tools reach the limit of optical resolution; while new test strategies are concurrently being introduced. Furthermore, the rising complexity and depth of logic, combined with the high compression ratio of the DFT scan architecture, makes fault diagnostics even more challenging and unreliable. This work will highlight some of the major challenges faced in the introduction of 10nm technology. It includes the intricacies of DFT fault diagnostics and the increasing limitations in electrical fault isolation, as the current available tools reach their minimum detection limits. This paper will present an innovative technique in performing fault isolation in our latest 10nm product to resolve 35% yield loss due to stuck-at-fault (SAF) logic failures during first silicon bring up. The biggest issue faced during debug apart from the fact that the devices were failing across all voltages and frequencies was lack of good diagnostics data that could lead to a viable suspect location. This prompted both DFT and FA teams to work together and develop innovative solutions to arrive to an accurate fault isolation. Lastly, this paper will also present a creative methodology of performing Laser Voltage Imaging (LVI) using scan chain integrity patterns, to debug the functional logic path, when conventional Laser Voltage Probing (LVP) using Automated Test Pattern Generation (ATPG) SAF patterns failed to arrive to a definitive conclusion due to tool resolution limitations.