Abstract

LVx, including Laser Voltage Imaging(LVI) and Laser Voltage Probing(LVP), is an indispensable optical failure analysis tool set for design debug and yield ramp-up. Although LVI and LVP together provide a good coverage for failure analysis cases involving scan-chain functionality testing, their applicability remains limited when addressing pulsed signals from logic circuits with ever growing complexity. Laser Voltage Tracing(LVT), as a recent addition to the LVx suite, provides a global map, highlighting the active region with low duty-cycle voltage transition pattern. In this paper, we present a case study of the detection of timing abnormality for a waveform feature with <0.1% duty cycle by applying LVT. Complemented by LVP and Soft Defect Localization (SDL), the fault was localized down to two interconnected logic gates. Resistive interconnection was confirmed with Physical Failure Analysis(PFA).

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