Solution for Accelerator Wall of HPC with HBM Integrated Packages

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With 4 billion-scaled daily-online- population in digital world, it becomes that the driving force of global economic is increasing the capital expenditure on cloud infrastructure deployed. As the architecture of high performance computing (HPC) is the trending on heterogeneous interconnection package (HIP) and three-dimension stacked platform as one of direction to migrate the accelerator wall. The routing path out of memory-bank is majority index reflecting on computing performance at band-width, data-rate latency, and power efficiency with rephrasing the Moore¡¦s Law on logic cell development. The numbers of packaged platform options is pop-up in semiconductor industry, momentum growing at on-and-off die scale packaging platform. The catalogue in industry is divided by three group: silicon bridge interposer, fan-out routed technology, substrate-selective replaced by silicon bridge die. In-depth reviewing the HIP packaging profile: First, silicon bridge interposer is strength on the surface of three-dimension thermal dissipation flow and equipping the less than 1/1 um L/S capability but mineral cost of silicon manufacturing is jeopardizing the ROI issue on expensive for consuming the deployed routed area. Second, fan-out routed technology is deploying the routing capability ranging from 2/2 um to 10/10 um L/S outline profile as flexible connection platform. Third, substrate-selective replaced by silicon bridge die is to leverage mature flip chip platform, it did provide the competitive pricing solution but the embedded die bridge technology is to constrain the power and computing at horizon scalable out deployment. This paper is to present the electrical metrics on HBM Integrated Packages at industry benchmark catalogue by simulation software analysis. The software modeling is to render the transportation performance of bit source deployed at high speed memory bank connection, and communicate the through-hole-via routing at fan-out scalable area, then reach to another logic cell chip bank. The strength is grouping the diversity transistor layout power-supplied at three-dimension building for avoiding the horizon transistor current constrain. The raised-module solution is key to jump across the accelerator wall with the advocating on bit-per-joule and ROI for next high performance computing.