Soldered chip reversed polarity detection based on semi-combinatorial attention and size-sensitive IoU

Abstract

Abstract Chips that have been automatically soldered may have defects such as short circuits, reversed polarity, offsets, and missing components. This paper proposes a reversed polarity detection algorithm (RPDNet) for soldered chips based on semi-combinatorial attention and size-sensitive IoU to solve the polarity reversal problem. To distinguish characters or patterns similar to polarity markings in the background, a semi-combination attention module (SCAM) is designed, which effectively distinguishes the subtle feature differences between polarity markings and background elements by integrating the long-range dependence of the self-attention mechanism and the local focusing ability of the general attention mechanism, thereby reducing misdetection of polarity markings. Aiming at the problem of blurred chip polarity markings, a differential pooling module (DPM) is proposed, which optimizes the downsampling process of fuzzy polarity markings by combining the differential features obtained from subtracting the results of max pooling from average pooling with features derived solely from average pooling, thereby reducing the information loss of fuzzy markings during the feature extraction process. In order to solve the lack of sensitivity of CIoU to the side length of the bounding box, a size-sensitive IoU(SIoU) is proposed. Through the size-sensitivity factor and area difference loss term, the model strengthens the focus on boundary regression and achieves faster and more accurate target positioning. Using the Chip-Set provided by the company for experiments and tests, the detection accuracy reached 97.79% and the processing speed reached 107 FPS.