Abstract
As semiconductor manufacturing migrates to more advanced technology nodes, accelerated aging effect for nanoscale devices poses as a key challenge for designers to find countermeasures that effectively mitigate the degradation and prolong system’s lifetime. Negative Bias Temperature Instability (NBTI) is emerging as one of the major reliability concerns. Two software tools for NBTI analyzing are proposed in this paper, one for transistor-level, and the other for gate-level. The transistor-level can be used to estimate the delay degradation due to NBTI effect very accurately, while the gate-level can be used for repeat analysis in circuit optimization because of its fast computing speed.
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