Software-controlled pipeline parity in GPU architectures for error detection

Abstract

Graphics Processing Units have been increasingly used to provide high-performance processing capabilities. Still, in some areas, such as avionics, it is subject to failures caused by radiation effects, leading to component failure and possible catastrophes. In such cases, fault tolerance techniques are mandatory to improve the reliability of GPUs. In this work, we propose a software-controlled pipeline parity hybrid fault tolerance technique to detect errors in the pipeline registers of an open-source NVIDIA G80 GPU architecture. Our proposed hardening technique enables software engineers to harden instructions at the assembly level and easily navigate the reliability versus cost design space. Results show that our approach can reduce errors by up to 57% at 11% cost in performance degradation and negligible costs in area.