SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors

Abstract

Speed binning of system-on-chips (SoCs) using conventional $F_{\mathrm {max}}$ test requires application of complex functional test patterns. Functional workload-based speed binning techniques incur high test-cost in terms of long test-time and complexity in functional test generation, and require high-end automatic test equipment. In this paper, we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the $F_{\mathrm {max}}$ values from a set of randomly tested die during wafer sort. The trained predictor is used to obtain the $F_{\mathrm {max}}$ for the remaining chips. The proposed flow has been demonstrated in an SoC benchmark circuit at 28 nm technology. For sufficient number of training samples, $F_{\mathrm {max}}$ is correctly predicted for 99% of the prediction samples.