Speed Binning Using Machine Learning And On-chip Slack Sensors

Abstract

Speed binning of integrated circuits using Fmax test of a SoC requires application of complex functional and structural test patterns. Today's test-pattern-based speed binning techniques incur high test cost in terms of long test time and requires significant effort to generate effective patterns. In this paper we propose a novel speed binning flow that uses path timing slacks, extracted with robust digital embedded sensor IPs, of selected critical/near-critical paths. We apply machine learning techniques to model a predictor considering the extracted slacks and the Fmax values from a set of randomly tested die during wafer sort. The proposed flow has been demonstrated in a SoC circuit at 28/32nm technology. The worst-case miss-binning of the predictor is within 6% of the nominal Fmax.