SOC Design for Wireless Communications

Abstract

A common denominator of system-on-chip (SOC) design is research of how to integrate a whole system on one silicon chip. The tutorial emphasizes design methods, architectures and circuits towards system level integration. It gives the basic knowledge and skills for designing small, low-power, embedded devices. Besides tackling issues of functionality, an important goal is to understand the balancing of production cost, development time, and performance of such devices. The complexity of these devices increases exponentially, and so does the effort of designing such systems. Only by using an appropriate design methodology which concentrates on reuse, executable specifications, and early error detection, these complexities can be mastered. The tutorial bundles these topics in order to provide a good understanding of all problems involved. Finally, it teaches how to design large systems and shows how to go from description and simulation to implementation and testing. A good SOC design flow assumes getting a design from the architectural level or RTL level to the chip layout. It should provide the designer with a working starting point for each stage of the design process. The tutorial describes such a methodology that relies on a library of configurable IP cores and custom hardware accelerators and satisfies the unique needs of wireless applications. The SOC design flow will be thoroughly examined with examples drawn from wireless communications.