Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices

Abstract

N-channel MOS transistors used in nMOS and in CMOS microelectronic circuits have a drain-to-source breakdown characteristic showing a negative resistance region. Activating this mode of operation leads to a drop in source-to-drain voltage and to a large drain current. Snap-back is not a four-layer (SCR, latch-up) phenomenon, but, like latch-up, can be initiated by current injection into the p-well, by avalanching junctions or by exposure to ionizing radiation. The sustaining voltage can be significantly below the drain-substrate avalanche voltage thereby limiting the maximum operating voltage. In this paper we present a qualitative model for snapback--local conductivity modulation occurring in the intrinsic base region of the parasitic bipolar transistor leading to regenerative feedback. Effects of process variations on the snap-back characteristics are presented as are triggering sensitivities to ionizing radiation.