Subnanometer Scaling of HfO[sub 2]/Metal Electrode Gate Stacks

Abstract

The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, reduction of the bottom interfacial layer (BIL) using interface engineering, thickness reduction of the dielectric, and use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the BIL with scaled /metal gates and 0.81 nm EOT using the BIL with scaled /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed. © 2004 The Electrochemical Society. All rights reserved.