Smart pixel VLSI architecture for embedded zerotree wavelet coding

Abstract

The smart pixel (SP) architecture is an array processor architecture which combines image capture and processing on a single device. Previously, an architecture to perform the discrete wavelet transform (DWT) within the SP array has been reported. A feature of the SP-DWT architecture is that the wavelet coefficients for each subband are not clustered together but are distributed in a certain pattern throughout the SP array. An encoder architecture for the embedded zerotree wavelet (EZW) algorithm has been reported which makes use of a modified EZW algorithm where instead of having to scan the whole wavelet coefficient in each pass of the algorithm, the modified algorithm only requires the scanning of one bit of the coefficient in each pass. In this paper, we present a scheme which takes advantage of the coefficient distribution in the SP array so that the bits of the coefficients are shifted out of the SP array in such a way that they can be input into the EZW encoder immediately with minimum buffering requirements.