VLSI decoder architecture for embedded zerotree wavelet algorithm

Abstract

In this paper, we present a hardware architecture to implement the decoder for the embedded zerotree wavelet (EZW) algorithm. The decoder architecture complements an encoder architecture for the EZW algorithm which has been reported recently. Similar to the reported encoder architecture, the proposed decoder architecture is regular and modular and is suitable for VLSI implementation. The input into the decoder architecture is the output data stream from the encoder architecture containing the significance map symbols and the successive-approximation quantization symbols of the EZW algorithm. The decoding for the EZW algorithm is formulated in view of the output data stream from the encoder and the corresponding VLSI architecture to implement the formulated requirements is presented. The proposed EZW decoder architecture together with the encoder architecture forms a basis for a scalable image or video coding system which is suitable for ASIC VLSI implementation.