Small-signal and power evaluation of novel BiCMOS-compatible short-channel LDMOS technology

Abstract

We describe a very short-channel 0.15-/spl mu/m LDMOS transistor with a breakdown voltage of up to 60 V, manufactured in a standard 0.35-/spl mu/m BiCMOS process. At 1900 MHz and a 12-V supply voltage, the 0.4-mm-gatewidth device with shortest drain drift region gives 100-mW output power P/sub 1dB/ at a drain efficiency of 43%. It has a transducer power gain of over 20 dB. The maximum current gain cutoff frequency f/sub T/ is 15 GHz, and the maximum available gain cutoff frequency f/sub MAX/ is 38 GHz. We show the dependence of f/sub T/, an f/sub MAX/ of gate and drain bias for transistors with different drain drift region length. The LDMOS process module does not affect the performance or the models of other devices. We present for the first time a simple way to create high-voltage high-performance LDMOS transistors for an RF power amplifier use even in a very downscaled silicon technology.