Small-Signal and Noise Model Determination for Double Polysilicon Self-Aligned Bipolar Transistors

A Caddemi,M Sannino

doi:10.1155/1994/38702

Abstract

In this paper, noise characterization and modeling of a double polysilicon self-aligned bipolar transistor are presented. The device has been characterized in terms of noise and scattering parameters by means of an original automatic noise figure measuring system only. Measurements have been performed over the 1–4 GHz frequency range and at different bias conditions. The extracted model refers to the performance of the chip device since the package and bond parasitics have been accurately de-embedded by proper calibration techniques.

Highlights

Printed in MalaysiaDipartimento di Ingegneria Elettrica--Universitt di Palermo, Laboratorio di Elettronica delle Microonde, Viale delle Scienze--90128, Palermo--ITALY
Consumer applications in the field of wireless communication systems at low microwave frequencies widely use silicon bipolar circuits due to the attractive features they offer in terms of performances, low cost technologies, chip count, and power consumption, which make them competitive alternatives to GaAs technologies
Today’s advanced bipolar processes often use double polysilicon self-aligned (PSA) schemes. They key issue is the selfalignment of the extrinsic base and the emitter, both of which are outdiffused and contacted with highly doped polysilicon layers separated by an oxide spacer

Summary

Printed in Malaysia

Dipartimento di Ingegneria Elettrica--Universitt di Palermo, Laboratorio di Elettronica delle Microonde, Viale delle Scienze--90128, Palermo--ITALY. Tel + + 39 91 590404, Fax + + 39 91 488452 (Received April 23, 1994; in final form May 23, 1994). Noise characterization and modelitg of a double polysilicon self-aligned bipolar transistor are presented. The device has been characterized in terms of noise and scattering parameters by means of an original automatic noise figure measuring system only. Measurements have been performed over the 1-4 GHz frequency range and at different bias conditions. The extracted model refers to the performance of the. Chip device since the package and bond parasitics have becn accurately de-embedded by proper calibration techniques The extracted model refers to the performance of the. chip device since the package and bond parasitics have becn accurately de-embedded by proper calibration techniques

INTRODUCTION

FIGURE Schematic cross section of the PSA transistor

Findings

CONCLUSIONS