Small Signal Capacitance and Glitch Power Estimation of Nanoscale MGDG MOSFET Based Circuits: A Device/Circuit Co-Design Approach

Abstract

Metal Gate Double Gate (MGDG) MOSFET has been proved to be vital in nanoscale regime for its leakage reduction and reduced sensitivity to process parameter variations in nanometer regime. This paper focuses on the glitch power minimization of nanoscale Logic/Memory circuits designed with MGDG MOSFET as device level solution. In this work, we have shown that MGDG MOSFET with intrinsic body has lower gate-drain capacitance there by reducing the magnitude of output overshoot or undershoot during signal transitioning events. We have done analysis of potential variation at critical nodes of SRAM cell designed with MGDG MOSFET using small signal capacitances as well as leakage currents and our analysis shows that read/write failures are reduced. Noise power is also minimized in devices using MGDG MOSFET due to reduced steady state charge injected into the body since minimum potential rise is observed during signal transition events. We have emphasized on low leakage, high performance robust circuits designed with the help of MGDG devices.