Slicer Architectures for Analog-to-Information Conversion in Channel Equalizers

Abstract

The scaling of analog-to-digital converter (ADC) power consumption with communication bandwidth imposes severe limits on its precision, which significantly impacts receiver performance. In this paper, we consider a “space-time” generalization of the flash architecture by allowing a fixed number of slicers to be dispersed in time (i.e., sampling offset) as well as space (i.e., amplitude), with the goal of investigating its capabilities for analog-to-information conversion (i.e., enabling reliable recovery of digital information, rather than faithful reproduction of the input signal) in the context of channel equalization for binary signaling over a dispersive channel. We first study standard symbol-spaced ADC with severe quantization constraints, estimating the minimum number of slicers needed to avoid error floors. We observe that the performance is sensitive to channel realization and sampling phase, which motivates a more flexible space-time architecture. Using ideas similar to those underlying compressive sensing, we prove that such architectures have no fundamental limitations in theory: randomly dispersing enough one-bit slicers over space and time does provide information sufficient for reliable equalization. We then focus on practical designs for symbol-spaced and fractionally-spaced sampling subject to a constraint on the number of slicers, and propose an algorithm for optimizing slicer thresholds, which significantly improves performance over a standard design.