Abstract
This paper aims to give an overview on some relevant aspects of the characterization of the SiO2/4H-SiC interface, considering the properties of this system both at the interface and inside the insulator. Nanoscale scanning probe microscopy (SPM) techniques were used to get insights on the homogeneity of the SiO2/SiC interface electrical properties upon metal-oxide-semiconductor (MOS) processing. On the other hand, capacitance and current measurements as a function of time were employed to investigate trapping states in MOS structures in the SiO2/4H-SiC system. In particular, time-dependent gate current measurements gave information on the near interface oxide traps (NIOTs) present inside the SiO2 layer. The impact of the observed trapping phenomena on SiO2/SiC metal oxide semiconductor field effect transistors (MOSFETs) operation is discussed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
