SiO2 Thickness Dependency of C-V Dispersion in Stacked Al/HfO2/SiO2/4H-SiC Capacitor

Abstract

The impact of a thin interfacial SiO2 layer inserted between HfO2 and SiC for the improvement of electrical property was investigated. Regarding the material choice of dielectric on SiC, two issues will be presented in this work. One demonstrates the border trap induced C-V frequency dispersion when HfO2 was directly deposited on SiC. The other deals with effect of carbon interstitial or bulk trap in SiC surface close to the SiC/SiO2 interface. The thickness of SiO2 interfacial layer is a critical issue. The defects induced by thicker SiO2 layer would affect the inversion region of substrate. With adopted ultrathin SiO2 (2 nm) layer between HfO2 and SiC, the remarkable frequency dispersion can be significantly reduced. The leakage current with ultrathin SiO2 layer reduced about two orders as compared with only HfO2 on SiC. The reliability of the device with ultrathin SiO2 layer was also improved.