Abstract

Due to their limited sensitive volumes for charge collection, silicon on insulator (SOI) technologies are good candidates for any microelectronic device operating in a space environment. While being insensitive to latchup phenomena, SOI devices may experience single-event effects (SEE's). Based on the analysis of the various structures of SOI transistors, charge collection mechanisms are presented. The different models proposed to analyze the sensitivity of CMOS SRAM cells are then discussed. The available data of SEU characterizations are finally compiled.

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