Single-electron transistor structures based on silicon-on-insulator silicon nanowire fabrication by scanning probe lithography and wet etching

Abstract

We propose a promising fabrication technology for single-electron transistors based on a silicon-on-insulator (SOI) nanowire fabricated by scanning probe lithography and KOH wet etching. The 10-nm-wide and 10-nm-high silicon nanowire is defined by scanning probe lithography and KOH wet etching process technology. Along the [100] direction on a (100) SOI silicon wafer, local oxidation was performed in ambient using highly doped Si cantilevers with a resistivity of 0.01–0.0025 Ω cm and a commercial atomic force microscope/scanning tunneling microscope instrument. Using the oxide pattern as a Si etching mask, the Si substrate was dipped in aqueous KOH solution, in which unoxidized regions are selectively etched by aqueous KOH orientation-dependent etching. The silicon nanowire was obtained by well-controlled overetching of 34 wt % at 40 °C for 50 s. The top gate, back gates and contact pads were defined by photolithography and dry etching. Statistics showing the reproducibility of this technique are also demonstrated.