Single‐pole multiple‐throw switches with defected ground structure low‐pass filter

Abstract

In this study, the authors present a novel concept for the design of single-pole multiple-throw (SPMT) switches using defected ground structure low-pass filter (DGS LPF). The DGS LPF produces enhanced inductance to compensate the parasitic capacitance of the control transistors. As a result, the SPMT switch will consume much less silicon area. The concept is experimentally validated with a single-pole double-throw (SPDT) switch and a single-pole four-throw (SP4T) switch in 65-nm CMOS. The active area of the SPDT and SP4T switches are less than 130 × 150 μm2 and 180 × 165 μm2, respectively.