Abstract
In this paper, a small-area and high-efficiency single-inductor multiple output (SIMO) boost converter with digital pulse-width modulation (DPWM) is proposed. The DPWM comprises a delay line using interlaced hysteresis delay cells (IHDCs) that occupy a small area while consuming a low power amount. These proposed IHDCs are applied to replace the conventional delay cells of the prior works for both the power and area reductions. Regarding the DC-DC converter, this technique comprises fewer digital blocks in the feedback path compared with the conventional DC-DC converter, and the DPWM architecture uses IHDCs. The purpose of the digital limiter block is to concede some helpful code for the DPWM. The IHDC topology used for delay in DPWM is of the simplest architecture. The high-side power switch gate drivers need individual phases which are generated by phase control. The Complementary Metal Oxide Semiconductor (CMOS)-fabrication process is 55 nm, with a standard supply voltage of 1.8 V and outputs of 2.2 and 2.4 V. The chip area is approximately 170 × 190 µm and its efficiency is 94.4%.
Highlights
The role of an efficient DC-DC converter in Internet of Things (IoTs) applications and electronic devices is important, while highly efficient power-management units are required for any electronic device in which the battery voltage is higher than the supply voltage
This scheme is the best solution for the issues of the close loop that occur in digital pulse-width modulation (DPWM) single-inductor multiple output (SIMO) DC-DC converters
The topology of interlaced hysteresis delay cells (IHDCs) greatly reduces the area of DPWM
Summary
The role of an efficient DC-DC converter in Internet of Things (IoTs) applications and electronic devices is important, while highly efficient power-management units are required for any electronic device in which the battery voltage is higher than the supply voltage. ADCs, digital controllers and counters, error amplifiers, external memories, reference voltage sources, large filter capacitors, and higher inductances that can lower switching frequencies require a large area. This work presents a SIMO DC-DC converter with an interlaced hysteresis delay cell (IHDC)-topology using digital pulse-width modulation (DPWM) that is highly efficient and comprises a small area; the transistor sizes are smaller than those of the conventional delay cells [19]. In [20,21], the scheme of SLH is used only in analog domain, but in [22], the scheme can apply in SIMO architectures with a digital control This scheme is the best solution for the issues of the close loop that occur in DPWM SIMO DC-DC converters.
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