Abstract
A superconducting front-end receiver operating in a wide frequency band from 10 to 40 Gb/s could increase the throughput of packet switches. Rapid Single Flux Quantum logic, which has the advantage of high-speed operation at medium integration levels, was used to build receiver components: a multiple bit-rate clock recovery circuit and a demultiplexer. Only 16 heading bits of the packet were required to read the clock frequency in a range from 22.5 to 45 Gb/s. Preliminary experiments showed single bit-rate clock recovery cell operation up to 35 GHz and /spl plusmn/17% bias current margins for a 1:2 demultiplexer. The interface between the receiver and semiconductor components is discussed.
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